ISSN 2456-0235

International Journal of Modern Science and Technology

INDEXED IN 

​​October-November 2021, Vol. 6, No. 10-11, pp. 171-174. 

​​​A High Speed and Low Leakage 12-T SRAM for Truncated Power Applications

P. S. Vinishya*, K. Solangkili
Department of Electronics and Communication Engineering, Arasu Engineering College, Chennai Main Road, Kumbakonam, India.

​​​*Corresponding author’s e-mail: er.vinishya@gmail.com

​Abstract

​High speed and low leakage constraints are put on the 12-T SRAM cell. Truncated power integrated circuits are massively fascinating for portable and wearable applications. A twelve-transistor SRAM circuit is proposed in this paper. The SRAM cells are designed with dual gate transistor for every column in order to achieve low leakage and high speed operation. An error margin is reduced up to 10% based on device size and capacitive load during read-out scheme. The data stability as well as read /write ability is based on standard topology which in turn reduces read /write delay.

Keywords: System on Chip; 12T SRAM; Integrated circuits; Wireless sensor application.

​References

  1. Upadhyay P, Nidhi A, Kar R, Mandal S, Ghoshal SP. Power and Stability Analysis of a Proposed 12T MTCMOS SRAM Cell for Low Power Devices”(2014).
  2. Upadhyay P, Sarthak G, Kar R, Mandal D, Ghoshal SP. Low Static and Dynamic Power MTCMOS Based 12T SRAM Cell for High Speed Memory System. 11th International joint Conference on Computer science & software engineering (JCSSE), 2014.
  3. Do AT, Jeremy YSL, Joshua YLL, Zhi-Hui K, Xiaoliang T, KiatSeng Y. An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. IEEE Transactions on Circuits and Systems-I, 2011;58:1252-63.
  4. Nam SK, Stark CD, Shi TZ, Sumeet K, Hamid RG, Taejoon P. Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area. IEEE Transactions on Very Large Scale Integration Systems 2012;20:2333-37.
  5. Sina H, Milad Z, Khosrow H. A 32kb 90nm 10T-cell Sub-threshold SRAM withImproved Read and Write SNM. 2013 21st Iranian Conference on Electrical Engineering (ICEE). 14-16 May 2013 Mashhad, Iran.
  6. Mohan S, Anitha A, Deepa R. Design of low power 8T SRAM cell. International Conference on Communication and Signal Processing, April 3-5, 2014.
  7. Basavaraj M, Kariyappa BS. Single Bit-line7T SRAM cell for Low Power and High SNM. 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s). 22-23 March 2013. Kottayam, India.
  8. Abdul Halim ISA, Basemu NH, Hassan SLM, Rahim AAA. Comparative Study on CMOS SRAM Sense Amplifiers using 90nm Technology., 2013 International Conference on Technology, Informatics, Management, Engineering & Environment (TIME-E 2013). June 23-26, 2013. Bandung, Indonesia.
  9. Achiranshu G, Tony THK. SRAM Array Structures for Energy Efficiency Enhancement. IEEE Transactions On Circuits And Systems-II: Express Briefs  2012;60:351-5 .
  10. Prashant U. Rajesh M, Niveditta T. Low Power Design of an SRAM Cell for Portable Devices. International Conference on Computer and Communication Technology (ICCCT). 17-19 Sept. 2010. Allahabad, India.