International Journal of Modern Science and Technology

INDEXED IN 

​​​​​​​​​​​​March 2018, Vol. 3, No. 3, pp 59-64. 

​​Design and Power analysis of Decoders for Memory Array Structure

K. Gavaskar, V. Malini
Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai – 638060. India.
​​​*Corresponding author’s e-mail: gavas.20@gmail.com

​Abstract

​Digital electronics circuits operate with digital signals so there performance is less subject to noise, signal attenuation and manufacturing tolerance. Digital system have prominent role in everyday life due to their ability to represent and manipulate discrete elements of information. Logic circuits for digital system may be combinational or sequential. A decoder is a combinational circuit that converts code into a set of signals. A binary code of n bits is capable of representing upto 2n distinct elements of coded information. The operation of the decoder may be clarified by the truth table. A decoder that generates the minterms of the function, together with an external OR gate that forms their logical sum, provides a hardware implementation of the function. A decoder with an enable input is referred to as decoder - demultiplexer. Three different decoders 1X2, 2X4 and 4X16 decoders are analyzed in this paper. Design metrics such as static power and dynamic power are taken into account. All the decoders were designed using SYNOPSYS EDA tool and simulated in 30nm technology. Simulation results shows that the 4X16 decoder has higher power dissipation than the other two decoders.

Keywords: Dynamic power; Static power; Decoder; Array structure; Memory.

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ISSN 2456-0235