ISSN 2456-0235

International Journal of Modern Science and Technology

INDEXED IN 

​​​​​International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 249-255. 

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​Reduction of Process Variation in Sub-threshold Logic Circuit using Adaptive Feedback Equalization  

R. Nithya*, P. Sathyaraj
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India. 
​​​*Corresponding author’s e-mail: nithyachitra61@gmail.com

​Abstract
Low energy or low powers are the primary constraint in the design of digital VLSI circuits in recent years. Minimum energy consumption can be achieved in digital circuits by operating it in the sub-threshold region. However this regime can only be achieved by proper body-biasing and transistor upsizing. Slow speed is the main drawback which can have a detrimental impact on the functionality of the circuits operating under low supply voltage. This becomes more frequent in scaled technology node where process variations are highly prevalent. Therefore mechanism to mitigate these timing errors in circuits is required. The proposal in this paper is to use variable threshold feedback equalizer circuit with combinational logic block to mitigate the timing constraint which can then be leveraged to reduce the propagation delay. As the part of analysis, a conventional D flip-flop is compared with a proposed equalized flip-flop using tanner EDA. The power and delay analysis of this feedback circuit is done using Xilinx software. 

​​Keywords: Feedback equalizer; Leakage energy component; Propagation delay; Sub-threshold.

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