ISSN 2456-0235

​​​​​International Journal of Modern Science and Technology, Vol. 2, No. 6, 2017, Pages 243-248.

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​Design of area efficient and low power carry select adder  

S. Sivaranjani*, G. Kavitha
Department of Electronics and Communication Engineering, Arasu Engineering College, Kumbakonam - 612501. India.
​​​*Corresponding author’s e-mail: sivaranjanisiva15@gmail.com

​Abstract
High performance digital adders with less power consumption and reduced area are a fundamental design issues for advanced processors.  Carry select adders is one of the fastest adder in many processors to perform fast arithmetic function.  The speed of operations such an adder is limited by carry propagation from input to output.  This project discusses about the implementation of Carry Select Adder (CSLA) with Binary to Excess-1 Code converters (BEC) and Multiplexer.  The BEC is used to improve the speed of addition.  The main advantage of BEC logic comes from the lesser number of logic gates than the Full Adder structure.  The reduced number of gates of this work offers the great advantage in the reduction of area and also the total power.  The CSLA are simulated  and  synthesized using  Xilinx  ISE 12.1v software. 

​​Keywords: Carry Select Adder; Ripple Carry Adder; Binary to Excess Code converters; Multiplexer.

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International Journal of Modern Science and Technology

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