INDEXED IN 

International Journal of Modern Science and Technology

​​​​​​Vol. 2, No. 10, 2017, pp. 328-336. 

​

​Low Power methodology for SRAM Memory using Dynamic Threshold MOS Transistor  

K. Gavaskar*, M. Sangavi, S. Ram Prasad, B. Sabari Manikandan
Department of Electronics and Communication Engineering, Kongu Engineering College, Erode, Tamilnadu – 638 060. India.
​​​*Corresponding author’s e-mail: gavas.20@gmail.com

​Abstract
Memory is a physical device capable of storing information temporarily or permanently. It is the most important part in complementary metal oxide semiconductor (CMOS) integrated circuit applications. It has been broadly used in VLSI circuits. SRAM is volatile in the conventional sense that data is eventually lost when the memory is not powered. Most important factor is that by applying various techniques its performance should not be changed and other factors such as area and speed should be taken into account. Thus in the design of SRAM cell using DTMOS, body terminal is connected to the gate terminal is a promising method for achieving enhanced performance without even modifying the existing structure of MOSFET. This is the major advantage of DTMOS as it is fully compatible with the conventional CMOS process. Hence SRAM memory cell by using DTMOS technique were designed and parameters like power, delay and power delay product has been analyzed and it is compared with the existing techniques. It can be used in personal computers, work stations, routers and peripheral equipment. On an average 33% of power has been reduced using DTMOS technique compared to conventional CMOS circuit. Thus the Proposed SRAM cell be used for used low power VLSI application. All the circuits were designed using TANNER EDA tool.

Keywords: Memory; Static Random Access Memory; Low power; Dynamic Threshold Logic. 

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ISSN 2456-0235