INDEXED IN 

​​​International Journal of Modern Science and Technology, 1(9), 2016, Pages 311-317. 


Low Power Flash ADC and DAC Optimized with Pull down Circuit Control

K. Abikayal, A. Sriram
Department of Electronics and Communication Engineering, Arasu Engineering College,

Kumbakonam – 612 501. India..

Abstract
Analog signal is characterized by the signal whose amplitude is continuously changing with respect to time while the amplitude and time is discrete in case of signal. The existing system describes the design of FLASH ADC using clocked digital comparator (CDC) will leads to setup and hold time violation and consumes power. The proposed system use latch based digital comparator with level based which reduces the power and increases the speed. ADC is controlled by a pull down network which triggers selected ADC as per the selection logic. The length of transistor is fixed and depending upon the width of transistor, internal references voltages are generated in the range of 0.63 to 1.02V.The proposed 4-bit flash ADC using CDC is designed using multiplexer based decoder and simulated with the help of Tanner-EDA tool in Tsmc 0.18 cmos technology.

​​Keywords: Multiplexer; Decoder; Clock Comparator; CMOS Switch.

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ISSN 2456-0235

International Journal of Modern Science and Technology